Memory cell arrays generally comprise active areas in which components of the memory cells are disposed. For example, the access transistor of a DRAM (dynamic random access memory) cell may be disposed in such an active area. Adjacent active areas may be separated from each other by isolation trenches that may be filled with an insulating material. A memory cell array further comprises word lines for controlling a read or a write operation as well as bit lines for transmitting information that is stored in the individual memory cells.
Usually, the bit lines and the word lines are arranged so as to intersect each other. In conventional approaches, the active areas have been implemented so as to be parallel to the bit lines or to the word lines. Alternatively, the active areas may be formed so as to run in a direction that is slanted with respect to the direction of the bit lines and the word lines, respectively.
In general, there is a need for further improving memory cell arrays. For example, attempts are made in order to further increase the packaging density of memory cells.